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第一階段
Verilog Synthesis

Topic

Course overview; Introduction to synthesis, ASIC&FPGA design flows, technology libraries, wire load modeling; timing constraints, synthesis software overview

Verilog Synthesis I: Data types, numbers, continuous assignments, procedural assignments, combinational logic and flip-flop inferences

Verilog Synthesis II: Operators, if-else and case statements, intentional and unintentional latch inference

Verilog Synthesis III: Synthesis of latches and flip-flops; blocking and nonblocking assignments; synthesis of loops, tasks, functions and parameters; finite state machine design

第二階段
Implementation Technologies and System-on-Chip Concepts

Topic

Programmable logic including FPGA: History, taxonomy, architectures & device examples

“Real World ASIC Design” (Source: NEC Electronics America. Used by permission) ASIC design flow, signal integrity, design size, tests, design for manufacturing (DFM)

System-on-Chip (SoC) Concepts: SoC components, on-chip and off-chip busses, IP blocks

SoC graphics subsystems; SoC design verification

第三階段
Digital System Timing Fundamentals

Topic

Why timing matters. Scaling of wires: The dark side of Moore’s law. Combinational timing modeling and analysis by critical path method

Sequential system timing: Clocks, register timing modeling. Setup and hold path analysis

Delay-locked and phase-locked loops, module port timing characterization (pin timing)

Reset timing: Synchronous or asynchronous? Timing-driven synthesis, timing optimizations: Clock skew and register retiming, static timing analysis.

第四階段
Advanced Digital System Timing

Topic

Synchronization and metastability

Synchronizer design

Multi-clock design techniques, signaling across clock domains

Self-timed logic design